When this bit is 1, an error has occurred (PE, BE, or BI) in the receive FIFO. When the Transmitter Empty bit is 1, it indicates that there are no bytes waiting to be transmitted and no byte currently being transmitted. When the Transmit Holding Register Empty bit is 1, it indicates that there are there are no bytes waiting to be transmitted, but there may be a byte currently being transmitted. When the Break Interrupt bit is set to 1, it indicates thata break has been received. When the Framing Error bit is set to 1, it indicates that a framing error occurred for the byte at the top of the receive FIFO. When the Parity Error bit is set to 1, it indicates that a parity error occurred for the byte at the top of the receive FIFO. When the Overrun Error bit is set to 1, it indicates that an overrun error occurred for the byte at the top of the receive FIFO. When the Data Ready bit is set to 1, it indicates that at least one byte is ready to be read from the receive FIFO or RBR. There is room for two more characters in the FIFO This setting has no effect if THRE_MODE_USER is disabled. Receive Trigger: These bits control the level at which the Received Data Available interrupt is triggered.
#Baud rate to bitrate converter full#
The FIFO is 50% full This setting has no effect if THRE_MODE_USER is disabled Transmit Empty Trigger: These bits control the level at which the Transmit Holding Register Empty interrupt is triggered 00: Transmit FIFO Reset: writing a 1 to this bit causes the transmit FIFO to be reset, and then continue normal operation Receive FIFO Reset: writing a 1 to this bit causes the receive FIFO to be reset, and then continue normal operation